Circuit Delay Modeling
Circuit Delay Modeling is a computational methodology within electronic design automation that characterizes the time lag of signal propagation through digital circuits by mathematically representing delay as a function of circuit topology, load conditions, and process-voltage-temperature variations.
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Publications
55.5K
Citations
2.7K
Authors
618
Institutions
Publications per year
2017–2026
88
Parents
1.3K
Model for Delay Faults Based Upon Paths
Gordon L. Smith · International Test Conference · 1985 · 710 citations
Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler et al. · 2000 · 611 citations · Full text
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Nanjing University of Information Science and Technology, China
19 publications · 484 citations
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618
University of California, Berkeley
Berkeley, United States
27 h-index
113 publications
9.2K citations
University of Michigan
Ann Arbor, United States
26 h-index
108 publications
5.5K citations
Intel (United States)
Santa Clara, United States
25 h-index
78 publications
3.2K citations
IBM (United States)
Armonk, United States
24 h-index
133 publications
6.7K citations
The University of Texas at Austin
Austin, United States
24 h-index
106 publications
6.6K citations
Stanford University
Stanford, United States
21 h-index
67 publications
2.8K citations

University of Minnesota
Minneapolis, United States
21 h-index
69 publications
4.7K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
21 h-index
69 publications
3.5K citations
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120 publications · 7.1K citations
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57 publications · 5.3K citations
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46 publications · 2.4K citations
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39 publications · 1.9K citations
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21 publications · 576 citations
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