Circuit Delay Modeling

Circuit Delay Modeling is a computational methodology within electronic design automation that characterizes the time lag of signal propagation through digital circuits by mathematically representing delay as a function of circuit topology, load conditions, and process-voltage-temperature variations.

1.3K

Publications

55.5K

Citations

2.7K

Authors

618

Institutions

Publications per year

2017–2026

88

Authors

2.7K

  1. DB
    David Blaauw

    University of Michigan, United States

    27 publications · 1.9K citations

    21

    h-index

  2. SS
    Sachin S. Sapatnekar

    University of Minnesota, United States

    28 publications · 2.2K citations

    20

    h-index

  3. EG
    Eby G. Friedman

    University of Rochester, United States

    25 publications · 1.4K citations

    18

    h-index

  4. LT
    Lawrence T. Pileggi

    Carnegie Mellon University, United States

    17 publications · 1.3K citations

    15

    h-index

  5. BR
    Blaise Ravelo

    Nanjing University of Information Science and Technology, China

    19 publications · 484 citations

    15

    h-index

1–5 of 2.7K

Venues

  1. 45

    h-index

  2. IEEE Journal of Solid-State Circuits

    57 publications · 5.3K citations

    29

    h-index

  3. 25

    h-index

  4. IEEE Transactions on Electron Devices

    39 publications · 1.9K citations

    20

    h-index

  5. 16

    h-index

1–5