Concepedia

M.S. Hrishikesh

MH

Statistics

Publications

7

Citations

1.2K

H-Index

7

Active since

2000

Affiliations

The University of Texas at Austin(Current)

PQ Corporation (Canada)

M.S. Hrishikesh is an author at The University of Texas at Austin specializing in computer science, computer architecture, and engineering.

Publications per year

2000–2003

7

Publications

7

Clock rate versus IPC

Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler et al. · 2000 · 611 citations · Full text

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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

M.S. Hrishikesh, Doug Burger, Norman P. Jouppi et al. · ACM SIGARCH Computer Architecture News · 2002 · 242 citations

, , +16

Static energy reduction techniques for microprocessor caches

Heather Hanson, M.S. Hrishikesh, Vikas Agarwal et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 104 citations

, , +17

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

M.S. Hrishikesh, Norman P. Jouppi, Keith I. Farkas et al. · 2003 · 91 citations

, , +16

Clock rate versus IPC

Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler et al. · ACM SIGARCH Computer Architecture News · 2000 · 76 citations · Full text

, , +17

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