Clock rate versus IPC

TLDR

The doubling of microprocessor performance every three years has been driven by more transistors per chip and superlinear scaling of processor clock rates with technology generation. The paper develops technology‑driven models for wire capacitance, wire delay, and microarchitectural component delay. Using these models, the authors simulate performance—estimating both clock rate and IPC—of an aggressive out‑of‑order microarchitecture scaled from 250 nm to 35 nm, evaluating three clock‑scaling targets and two microarchitecture‑scaling strategies (pipeline and capacity scaling). The results show that performance growth of conventional microarchitectures will slow, with no scaling strategy achieving annual improvements above 12.5%, far below the 50–60% gains historically observed.

Abstract

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance—estimating both clock rate and IPC —of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.