EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsTest ConstructionBuilt-in Self-testDesign For TestabilityElectrical System TestingFault DetectionTiming AnalysisDelay Fault TestingFault CoverageFault SimulationLogic Built-in Self-testLogic Gate DelayTest GenerationTiming Faults
The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Model for Delay Faults Based Upon Paths
Gordon L. Smith · International Test Conference · 1985 · 710 citations