Logic Gate Delay

Logic Gate Delay is the propagation delay inherent to a logic gate, defined as the time interval between the application of a signal transition at its input and the corresponding output response, distinguishing it from other timing delays in digital circuits by being specific to the physical switching characteristics of the gate's implementation.

197

Publications

7.5K

Citations

613

Authors

147

Institutions

Publications per year

2017–2026

9

Authors

613

  1. MA
    Massimo Alioto

    National University of Singapore, Singapore

    7 publications · 187 citations

    7

    h-index

  2. SK
    S. Kotani

    Fujitsu (Japan), Japan

    5 publications · 140 citations

    5

    h-index

  3. ST
    S. Takada

    Electrotechnical Institute, Poland

    5 publications · 91 citations

    5

    h-index

  4. HN
    Hiroshi Nakagawa

    University of Oklahoma Health Sciences Center, United States

    5 publications · 91 citations

    5

    h-index

  5. JD
    John D. Cressler

    Georgia Institute of Technology, United States

    5 publications · 131 citations

    5

    h-index

1–5 of 613

Venues

  1. IEEE Journal of Solid-State Circuits

    25 publications · 1.1K citations

    17

    h-index

  2. IEEE Electron Device Letters

    14 publications · 414 citations

    13

    h-index

  3. IEEE Transactions on Electron Devices

    10 publications · 247 citations

    10

    h-index

  4. 8

    h-index

  5. Applied Physics Letters

    6 publications · 97 citations

    6

    h-index

1–5