Logic Gate Delay
Logic Gate Delay is the propagation delay inherent to a logic gate, defined as the time interval between the application of a signal transition at its input and the corresponding output response, distinguishing it from other timing delays in digital circuits by being specific to the physical switching characteristics of the gate's implementation.
197
Publications
7.5K
Citations
613
Authors
147
Institutions
Publications per year
2017–2026
9
Parents
197
On the detection of delay faults
A.K. Pramanick, S.M. Reddy · 2003 · 168 citations
Engineering, Computer Engineering, Electrical Engineering +15
1–5 of 197
613
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University of Oklahoma Health Sciences Center, United States
5 publications · 91 citations
5
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5
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1–5 of 613
147
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
13 h-index
72 publications
1.9K citations
IBM (United States)
Armonk, United States
11 h-index
57 publications
1.5K citations
Fujitsu (Japan)
Kawasaki, Japan
8 h-index
40 publications
1.1K citations
University of Siena
Siena, Italy
6 h-index
19 publications
557 citations

University of Waterloo
Waterloo, Canada
6 h-index
11 publications
698 citations
Hitachi (Japan)
Tokyo, Japan
6 h-index
36 publications
937 citations
Hewlett-Packard (United States)
Palo Alto, United States
5 h-index
8 publications
377 citations
University of Southern California
Los Angeles, United States
5 h-index
13 publications
770 citations
1–8 of 147
25 publications · 1.1K citations
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14 publications · 414 citations
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10 publications · 247 citations
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8 publications · 694 citations
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6 publications · 97 citations
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