S. Pullela

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Jessica Qian, S. Pullela, L.T. Pillage · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1994 · 334 citations

Engineering, Vlsi Design, Computer Architecture +18

Skew And Delay Optimization For Reliable Buffered Clock Trees

S. Pullela, N. Menezes, J. Omar et al. · Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) · 2005 · 108 citations

Engineering, Vlsi Design, Clock Recovery +13

Reliable non-zero skew clock trees using wire width optimization

S. Pullela, Noel Menezes, L.T. Pillage · 1993 · 96 citations · Full text

Library-less synthesis for static CMOS combinational logic circuits

S. V. Gavrilov, A. Glebov, S. Pullela et al. · International Conference on Computer Aided Design · 1997 · 45 citations

Logic Synthesis, Engineering, Vlsi Design +11

Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer

C.L. Ratzlaff, S. Pullela, L.T. Pillage · 1992 · 45 citations

Electrical Engineering, Polynomial Function, Engineering +14