IEEE Electron Device Letters · 2004 · 131 citations · 11 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsSemiconductor DevicesSemiconductor MaterialsDevice ModelingInterface EngineeringInterface ModelingMetal-oxide-semiconductor Field-effect TransistorsSemiconductor InterfacesThermal Properties Of SemiconductorsAnnealingAnnealing EffectsAnnealing Temperature EffectsDielectric InterfacesDielectric-semiconductor InterfacesFermi LevelFermi Level PinningMetal Gates
The dependence of the metal-gate work function on the annealing temperature is experimentally studied. We observe increased Fermi-level pinning of the metal-gate work function with increased annealing temperature. This effect is more significant for SiO/sub 2/ than for HfO/sub 2/ gate dielectric. A metal-dielectric interface model that takes the role of extrinsic states into account is proposed to explain the work function thermal instability. This letter provides new understanding on work function control for metal-gate transistors and on metal-dielectric interfaces.
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Fermi level pinning at the polySi/metal oxide interface
Chris Hobbs, L.M. Fonseca, V. Dhandapani et al. · 2004 · 111 citations