P. Ranade

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

Extremely scaled silicon nano-CMOS devices

Leland Chang, Yang‐Kyu Choi, Daewon Ha et al. · Proceedings of the IEEE · 2003 · 280 citations

Engineering, Electrical Engineering, Materials Science +17

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Engineering, Computer Engineering, Electrical Engineering +17

An adjustable work function technology using Mo gate for CMOS devices

R. Lin, Qiang Lu, P. Ranade et al. · IEEE Electron Device Letters · 2002 · 189 citations

Engineering, Electrical Engineering, Materials Engineering +17

Dual work function metal gate CMOS technology using metal interdiffusion

I. Polishchuk, P. Ranade, Tsu-Jae King et al. · IEEE Electron Device Letters · 2001 · 176 citations

Engineering, Electrical Engineering, Materials Science +17