A. Cappellani

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm

R. Rios, A. Cappellani, M Armstrong et al. · IEEE Electron Device Letters · 2011 · 335 citations

Engineering, Electrical Engineering, Electronic Materials +10

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Engineering, Computer Engineering, Electrical Engineering +17

The ultimate CMOS device and beyond

Kelin J. Kuhn, Uygar E. Avci, A. Cappellani et al. · 2012 · 81 citations

Engineering, Computer Engineering, Electrical Engineering +17

Processing and characterisation of sol–gel deposited Ta2O5 and TiO2–Ta2O5 dielectric thin films

A. Cappellani, Joseph L. Keddie, N.P. Barradas et al. · Solid-State Electronics · 1999 · 41 citations

Natural Sciences, Materials Engineering, Materials Science +12