Kelin J. Kuhn

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

Considerations for Ultimate CMOS Scaling

Kelin J. Kuhn · IEEE Transactions on Electron Devices · 2012 · 661 citations

Hardware Security, Electrical Engineering, Engineering +10

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 654 citations

Electrical Engineering, Engineering, Nanoelectronics +10

Process Technology Variation

Kelin J. Kuhn, M.D. Giles, D. Becher et al. · IEEE Transactions on Electron Devices · 2011 · 360 citations

Law Technology Scaling, Engineering, Vlsi Design +19

Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm

R. Rios, A. Cappellani, M Armstrong et al. · IEEE Electron Device Letters · 2011 · 334 citations

Electrical Engineering, Engineering, Applied Physics +8