Circuit relevant well charging from metal antenna and its degradation on digital MOS transistor reliability

Abstract

In this work digital MOS transistors of three different process nodes are investigated for reliability degradation from plasma induced charging (PID). It is demonstrated that a charging of triple well/dual well configurations lead to significantly increased gate oxide leakage currents of connected MOS transistors which are placed in adjacent well regions. This has not been yet investigated in such detail with test structures which are product relevant over a wide range of well sizes and different areas of large metal antenna. The characterization of well charging requires a new definition of the antenna ratio for the comparison of experimental reliability degradation results between process nodes. Findings can be directly applied to product layout.