J.M. Luchies

Grounded-gate nMOS transistor behavior under CDM ESD stress conditions

K. Verhaege, C. Russ, J.M. Luchies et al. · IEEE Transactions on Electron Devices · 1997 · 27 citations

Device Modeling, Electrical Engineering, Engineering +11

Identification of plasma-induced damage conditions in VLSI designs

P. Simon, J.M. Luchies, W. Maly · IEEE Transactions on Semiconductor Manufacturing · 2000 · 20 citations

Electrical Engineering, Plasma Electronics, Engineering +9

Relation between product yield and plasma process induced damage

J.M. Luchies, P. Simon, F.G. Kuper et al. · 2002 · 17 citations

Electrical Engineering, Engineering, Process Dependent Parameter +10

Antenna ratio definition for VLSI circuits [plasma etch damage]

P. Simon, J.M. Luchies, W. Maly · 2003 · 14 citations

Ic Layouts, Electrical Engineering, Engineering +12

NMOS Transistor behaviour under CDM stress conditions and relation to other ESD models

K. Verhaege, J.M. Luchies, Christian Russ et al. · Data Archiving and Networked Services (DANS) · 1995 · 14 citations

Device Modeling, Electrical Engineering, Engineering +8