C. Russ - Concepedia

Author

C. Russ

Infineon Technologies (Germany)

Also Known As

C. Russ, C.C. Russ, Corbin Russ, Marjory Mcfarlane

Publications

852

Citations

H-Index

Concepts

All Affiliations

Infineon Technologies (Germany)IMEC Texas Instruments (United States)IBM (United States)Centre National de la Recherche Scientifique

About

C. Russ is an author at Infineon Technologies (Germany) specializing in electrical engineering, microelectronics, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	18	22	763
2	Computer Engineering	13	13	500
3	Applied Physics	7	7	309
4	Education	1	1	13
5	Medicine	1	1	55

C. Russ

Publications

775

Citations

H-Index

Page 1

	Year	Citations
Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides M. Mergens, C. Russ, K. Verhaege, EngineeringVlsi DesignPower ElectronicsElectromagnetic CompatibilitySemiconductor Device	2004	102
Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies M. Mergens, C. Russ, K. Verhaege, IEEE Transactions on Device and Materials Reliability EngineeringRadio FrequencyPower ElectronicsSemiconductor DeviceElectromagnetic Compatibility	2005	98
GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes C. Russ, M. Mergens, K. Verhaege, Electrical Overstress/Electrostatic Discharge Symposium Low-power ElectronicsHardware SecurityElectrical EngineeringGgnmos Triggered SiliconDeep Sub-micron Cmos	2001	69
Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing C. Russ, Karlheinz Bock, Mahmoud Rasras, Electrical EngineeringNon-uniform TriggeringEngineeringMedicineBias Temperature Instability	2002	55
A compact model for the grounded-gate nMOS behaviour under CDM ESD stress C. Russ, K. Verhaege, Karlheinz Bock, Device ModelingElectrical EngineeringCdm Esd StressEngineeringVlsi Design	2005	43
Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling M. Mergens, K. Verhaege, C. Russ, Electrical Overstress/Electrostatic Discharge Symposium Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignDesign Techniques	2001	43
Understanding the optimization of sub-45nm FinFET devices for ESD applications David Trémouilles, S. Thijs, C. Russ, Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignSelective Epitaxial Growth	2007	35
Circuit design issues in multi-gate FET CMOS technologies C. Pacha, K. von Arnim, T. Schulz, Finfet-based Miller OpampElectrical EngineeringEngineeringVlsi DesignNanoelectronics	2006	29
Wafer cost reduction through design of high performance fully silicided ESD devices K. Verhaege, C. Russ Electrical EngineeringSilicide Blocked DesignsEngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2002	27
Grounded-gate nMOS transistor behavior under CDM ESD stress conditions K. Verhaege, C. Russ, J.M. Luchies, IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringEngineeringSocketed CdmNanoelectronics	1997	27

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