A compact model for the grounded-gate nMOS behaviour under CDM ESD stress

Abstract

The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. The optimal gate length for CDM protection in advanced submicron technologies is discussed.