IEEE Transactions on Nuclear Science · 2006 · 18 citations · 6 references
Hardware SecurityElectrical EngineeringNew Latch DesignEngineeringVlsi DesignCircuit DesignLatch DesignVlsi ArchitectureElectronic DesignComputer EngineeringFormal MethodsComputer ArchitectureDigital Circuit DesignDice Latch DesignMicroelectronicsFormal Verification
A new latch design using Cascode-Voltage Switch Logic gates is evaluated for single event (SE) environments. The latch design is based on the DICE latch design, but with CVSL gates. Calibrated 3D device models for an IBM 130 nm technology were used for mixed-mode simulations of the latch for SE evaluations. Simulation results show that the latch is immune to charge deposition on multiple nodes. The proposed design does require a 60% increase in area and double the power, but is faster than conventional DICE-based latch design
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Cascode voltage switch logic: A differential CMOS logic family
L.G. Heller, W. Paul Griffin, Jack Davis et al. · 1984 · 481 citations
Comparison of error rates in combinational and sequential logic
S. Büchner, M.P. Baze, David J. Brown et al. · IEEE Transactions on Nuclear Science · 1997 · 238 citations