Low-power Latch Design

Low-Power Latch Design is a circuit-level methodology within digital system design that specifically addresses the minimization of power consumption in latch architectures through optimized transistor sizing, clock gating, or voltage scaling techniques while maintaining signal integrity and timing constraints.

296

Publications

13.5K

Citations

899

Authors

271

Institutions

Publications per year

2017–2026

Parents

Low-power Digital Circuit Design

Publications

296

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

John F. Dickson · IEEE Journal of Solid-State Circuits · 1976 · 1.7K citations

Engineering, Computer Engineering, Electrical Engineering +17

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Vladimir Stojanović, Vojin G. Oklobdzija · IEEE Journal of Solid-State Circuits · 1999 · 618 citations

Engineering, Computer Engineering, Computer Science +17

The StrongARM Latch [A Circuit for All Seasons]

Behzad Razavi · IEEE Solid-State Circuits Magazine · 2015 · 519 citations

Engineering, Computer Engineering, Electrical Engineering +13

Flow-through latch and edge-triggered flip-flop hybrid elements

H. Partovi, R. Burd, Umer Salim et al. · 2002 · 308 citations

Engineering, Computer Engineering, Computer Science +16

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

Xiyuan Tang, Linxiao Shen, Begum Kasap et al. · IEEE Journal of Solid-State Circuits · 2020 · 276 citations

Engineering, Computer Engineering, Electrical Engineering +16

1–5 of 296

Authors

899

ZH
Zhengfeng Huang
Hefei University of Technology, China
14 publications · 635 citations
13
h-index
AY
Aibin Yan
Anhui University, China
15 publications · 734 citations
13
h-index
JC
Jie Cui
Anhui University, China
9 publications · 445 citations
9
h-index
XW
Xiaoqing Wen
Kyushu Institute of Technology, Japan
9 publications · 443 citations
9
h-index
VG
Vojin G. Oklobdzija
University of California, Davis, United States
9 publications · 850 citations
9
h-index

1–5 of 899

Institutions

271

1–8 of 271

Venues

IEEE Journal of Solid-State Circuits
31 publications · 4K citations
21
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
16 publications · 1.3K citations
15
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
10 publications · 525 citations
10
h-index
IEEE Transactions on Circuits & Systems II Express Briefs
11 publications · 490 citations
10
h-index
Electronics Letters
9 publications · 252 citations
9
h-index

1–5