Thinning, stacking, and TSV proximity effects for Poly and High-K/Metal Gate CMOS devices in an advanced 3D integration process

Abstract

An advanced 3D integration process featuring through silicon via (TSV) and chip-on-wafer (CoW) technologies has been demonstrated. Using this 3D process, Poly and High-K/Metal Gate (HKMG) CMOS wafers have been successfully thinned and stacked, showing little to no degradation in the process. The effect of TSV induced mechanical stress on ΔIdsat for HKMG is found to be smaller as compared to Poly Gate devices for the same channel length (ΔIdsat ratio of HKMG to Poly is ~0.3 and ~0.5 for PMOS and NMOS, respectively). In addition, we show that ΔIdsat for HKMG device is proportional to TSV diameter square, independent of TSV orientation, device polarity, and device distance from TSV.