P. Morrow

Die Stacking (3D) Microarchitecture

Bryan Black, Daniel Pantuso, Paul A. Reed et al. · 2006 · 598 citations

Hardware Security, 3D Ic Architecture, Electrical Engineering +13

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

P. Morrow, Choon-Ho Park, Shriram Ramanathan et al. · IEEE Electron Device Letters · 2006 · 166 citations

Materials Science, 3D Ic Architecture, Electrical Engineering +15

3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

ChingYao Huang, G. Dewey, Ehren Mannebach et al. · 2020 · 106 citations

Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts

M. Radosavljević, ChingYao Huang, Rohit Galatage et al. · 2023 · 30 citations

Engineering, Vlsi Design, Nanocomputing +16

Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking

M. Kobrinsky, J. D Silva, Ehren Mannebach et al. · 2023 · 16 citations