3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

Abstract

We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked dual metal gate process. Both top NMOS and bottom PMOS show high on-state performance and superior short channel control. A functional CMOS inverter is also demonstrated with well-balanced voltage transfer characteristics. The 3-D self-aligned stacked CMOS nanoribbon transistor is demonstrated as a promising transistor architecture to continue Moore’s law scaling.