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Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

DOI

10

Citations

13

References

2013

Year

C. Fenouillet-Béranger, P. Perreau, T. Benoist, C. Richier, S. Haendler, J. Pradelle, J. Bustos, P. Brun, L. Tosti, O. Weber,
Solid-State Electronics

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2010

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Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

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23

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