Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

ESD in silicon integrated circuits

Microelectronics Reliability · 1996 · 442 citations

Engineering, Electrical Engineering, Microelectronics +9

Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Jean-Philippe Noël, Olivier Thomas, Marie-Anne Jaud et al. · IEEE Transactions on Electron Devices · 2011 · 183 citations

Engineering, Computer Engineering, Electrical Engineering +17

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Weber, O. Faynot, F. Andrieu et al. · 2008 · 159 citations

Engineering, Electrical Engineering, Materials Science +17

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

C. Fenouillet-Béranger, S. Denorme, P. Perreau et al. · Solid-State Electronics · 2009 · 133 citations

Engineering, Computer Engineering, Electrical Engineering +11

Efficient multi-V<inf>T</inf> FDSOI technology with UTBOX for low power circuit design

C. Fenouillet-Béranger, Olivier Thomas, P. Perreau et al. · 2010 · 70 citations

Engineering, Computer Engineering, Electrical Engineering +8