Publication | Closed Access
FDSOI devices with thin BOX and ground plane integration for 32nm node and below
39
Citations
2
References
2008
Year
Unknown Venue
EngineeringVlsi DesignThin BoxDevice IntegrationFdsoi DevicesIntegrated CircuitsGround Plane IntegrationElectromagnetic CompatibilityInterconnect (Integrated Circuits)Fully-depleted SoiAdvanced Packaging (Semiconductors)NanoelectronicsElectronic Packaging3D Ic ArchitectureElectrical EngineeringBias Temperature InstabilityComputer EngineeringGround PlaneMicroelectronicsLow-power ElectronicsDifferent BoxApplied PhysicsSemiconductor Memory
In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.
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