2008 · 39 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSystem-on-chip DesignDevice ModelingDevice SimulationIntegrated Circuit DesignIntegrated Circuit DevicesNanoelectronicsVery-large-scale Integration LayoutLarge-area ElectronicsThrough-silicon Vias
In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.
2
A Cost-Effective Low Power Platform for the 45-nm Technology Node
E. Josse, S. Parihar, Olivier Callen et al. · 2006 · 33 citations
Engineering, Computer Engineering, Electrical Engineering +11