2012 · 19 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignPhysical DesignPower ManagementPower OptimizationFabricationHigh PerformanceLow-power Cmos DesignPower ConsumptionPower EfficiencyPower Management DesignPower Management TechniquesResponsiveness
Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar bulk CMOS. At 28nm, we find that planar FD more than matches the peak performance of “G”-type bulk technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. FD implementation of a representative design offers 1.6×–7× speedup compared to bulk across a range of supply voltages.
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Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot, F. Andrieu, O. Weber et al. · 2010 · 104 citations