Giorgio Cesana

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

D. Jacquet, F. Hasbani, Philippe Flatresse et al. · IEEE Journal of Solid-State Circuits · 2014 · 128 citations

Low-power Electronics, Energy Efficiency Optimization, Electrical Engineering +15

UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency

Philippe Magarshack, Philippe Flatresse, Giorgio Cesana · Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 · 2013 · 72 citations

Engineering, Vlsi Design, Energy Efficiency +18

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

Philippe Flatresse, Bastien Giraud, Jean-Philippe Noël et al. · 2013 · 71 citations

Low-power Electronics, Electrical Engineering, Engineering +11

2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI

D. Jacquet, Giorgio Cesana, Philippe Flatresse et al. · 2013 · 20 citations

Low-power Electronics, System On Chip, Electrical Engineering +14

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

Bertrand Pelloux-Prayer, Milovan Blagojević, Olivier Thomas et al. · 2012 · 19 citations