Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Kangguo Cheng, A. Khakifirooz, P. Kulkarni, +33

Low-power ElectronicsElectrical EngineeringSige RsdEngineeringVlsi Design +10

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Qijiong Liu, A. Yagishita, N. Loubet, +34

Low-power ElectronicsDevice ModelingElectrical EngineeringUtbb StructureEngineering +13

A 0.063 µm<sup>2</sup> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

V. Basker, T. Standaert, Hikaru Kawasaki, +37

Novel Integration SchemeEngineeringVlsi DesignMicroscopyPattern Transfer +19

UTBB FDSOI transistors with dual STI for a multi-V<inf>t</inf> strategy at 20nm node and below

L. Grenouillet, M. Vinet, J. Gimbert, +39

Electrical EngineeringUtbb Fdsoi TransistorsEngineeringVlsi DesignVlsi Architecture +9

Impact of back bias on ultra-thin body and BOX (UTBB) devices

Q. Liu, F. Monsieur, Arvind Kumar, +39

V BbElectrical EngineeringBiomedical SensorsEngineeringBack Bias +11

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

A. Khakifirooz, Kangguo Cheng, Toshiharu Nagumo, +33

Semiconductor TechnologyElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Contact Strain +12

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Takashi Yamashita, V. Basker, T. Standaert, +41

Symposium on VLSI Technology

Electrical EngineeringAdvanced Fin FormationEngineeringVlsi DesignSelf-heating Correction +10

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

Kangguo Cheng, A. Khakifirooz, P. Kulkarni, +28

Symposium on VLSI Technology

Electrical EngineeringNovel Integration SchemeEngineeringNew Integration SchemeEtsoi Devices +13

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

A. Khakifirooz, Kangguo Cheng, P. Kulkarni, +36

EngineeringVlsi DesignSilicon On InsulatorInterconnect (Integrated Circuits)Future Low Power +15

Extremely thin SOI (ETSOI) technology: Past, present, and future

Kangguo Cheng, A. Khakifirooz, P. Kulkarni, +25

EngineeringVlsi DesignDevice IntegrationComputer ArchitectureMaterial Innovation +17