Embedded deterministic test for low-cost manufacturing

Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, N. Tamarapalli, Jerzy Tyszer, Jun Qian

IEEE Design & Test of Computers · 2003 · 64 citations · 12 references

Concepts

Abstract

You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.

References

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