Embedded Deterministic Test

Embedded Deterministic Test is a deterministic built-in self-test methodology that enables on-chip generation of precise, algorithmically defined test patterns for targeted defect detection, distinguishing itself from stochastic or pseudorandom approaches by ensuring complete control over test stimulus content and timing.

24

Publications

1.7K

Citations

53

Authors

17

Institutions

Publications per year

2017–2026

1

Variants

Edt

Authors

53

  1. JT
    Jerzy Tyszer

    Poznań University of Technology, Poland

    12 publications · 1.3K citations

    12

    h-index

  2. JR
    Janusz Rajski

    Mentor Technologies, United States

    10 publications · 864 citations

    10

    h-index

  3. NM
    Nilanjan Mukherjee

    Mentor Technologies, United States

    9 publications · 1.2K citations

    9

    h-index

  4. GM
    Grzegorz Mrugalski

    Poznań University of Technology, Poland

    8 publications · 614 citations

    8

    h-index

  5. MK
    Mark Kassab

    Mentor Technologies, United States

    6 publications · 1K citations

    6

    h-index

1–5 of 53

Venues

  1. 5

    h-index

  2. 2

    h-index

  3. 2

    h-index

  4. 1

    h-index

  5. IEEE Design & Test of Computers

    1 publications · 64 citations

    1

    h-index

1–5