Embedded Deterministic Test
Embedded Deterministic Test is a deterministic built-in self-test methodology that enables on-chip generation of precise, algorithmically defined test patterns for targeted defect detection, distinguishing itself from stochastic or pseudorandom approaches by ensuring complete control over test stimulus content and timing.
24
Publications
1.7K
Citations
53
Authors
17
Institutions
Publications per year
2017–2026
1
Variants
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Parents
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Embedded deterministic test for low cost manufacturing test
J. Rajski, Jerzy Tyszer, Mark Kassab et al. · 2003 · 402 citations
Engineering, Computer Engineering, Electrical Engineering +13
Embedded deterministic test for low-cost manufacturing
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee et al. · IEEE Design & Test of Computers · 2003 · 64 citations
1–5 of 24
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Mentor Technologies
Tulsa, United States
12 h-index
48 publications
7K citations

Poznań University of Technology
Poznan, Poland
10 h-index
20 publications
1.9K citations
Siemens (Hungary)
Budapest, Hungary
7 h-index
26 publications
2.3K citations
Duke University
Durham, United States
3 h-index
4 publications
145 citations
Intel (United States)
Santa Clara, United States
2 h-index
10 publications
351 citations
University of Stuttgart
Stuttgart, Germany
2 h-index
6 publications
243 citations
Aptiv (United States)
Troy, United States
2 h-index
2 publications
92 citations

National Taiwan University
Taipei, Taiwan
2 h-index
4 publications
118 citations
1–8 of 17
5 publications · 639 citations
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2 publications · 67 citations
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2 publications · 86 citations
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1 publications · 14 citations
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1 publications · 64 citations
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