Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/

Abstract

In this work, we describe a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory device. The device consists of a metal-oxide-semiconductor field-effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric. The trap formation method provides for precise control of the thicknesses of the top (control) and bottom (tunneling) oxide layers which sandwich the charge-traps, via thermal oxidation. This memory device exhibits write/erase speed/voltage and retention time superior to previously reported nano-crystal or charge-trap memory devices. A detailed description of the novel process for fabricating the Ge charge-trap MOS memory is given, along with the resultant memory-cell performance characteristics.