2015 · 11 citations · 7 references
EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ReliabilityReliabilityReliability AssuranceReliability ModelingSemiconductor ReliabilityCmos ReliabilityEnhancement-mode TransistorsEnvironmental ReliabilityPackage ReliabilityPackage-level ReliabilityPackaging Reliability TestingPackaging-induced ReliabilityReverse Bias Characteristics
Reliability testing of GaN transistors continues to accumulate with positive results. In this paper, we build upon previous studies [1-7], providing new reliability data on commercially available enhancement mode GaN transistors under a wide variety of stress conditions. The first section reports data on long-term, large sample size qualification testing under high temperature reverse bias (HTRB) and high temperature gate bias (HTGB). Environmental reliability data is also shown, including temperature cycling and humidity. The second section provides failure rate predictions using acceleration factors derived by stressing devices outside of normal gate and drain voltage stress conditions. In the last section, we discuss the reliability advantages of wafer level chipscale (WLCS) packaging compared to conventional MOSFET packages.
7
Trapping effects in GaN and SiC microwave FETs
S.C. Binari, P. B. Klein, T.E. Kazior · Proceedings of the IEEE · 2002 · 454 citations