Snapback Device Protection
Snapback Device Protection is a semiconductor-based electrostatic discharge (ESD) protection mechanism that operates by exploiting the inherent bipolar transistor action within a MOSFET to trigger a low-impedance conduction path during voltage overstress events, thereby preventing damage to sensitive integrated circuit components.
39
Publications
972
Citations
133
Authors
37
Institutions
Publications per year
2017–2026
7
39
A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
C. Russ, K. Verhaege, Karlheinz Bock et al. · 2005 · 43 citations
Engineering, Electrical Engineering, Electronic Materials +16
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133
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37
Texas Instruments (United States)
Dallas, United States
9 h-index
23 publications
462 citations
IMEC
Leuven, Belgium
6 h-index
29 publications
810 citations

National Yang Ming Chiao Tung University
Hsinchu, Taiwan
4 h-index
11 publications
349 citations
Analog Devices (United States)
Norwood, United States
3 h-index
12 publications
288 citations
Motorola (United States)
Schaumburg, United States
3 h-index
12 publications
384 citations
University College London
London, United Kingdom
2 h-index
2 publications
49 citations

University of Central Florida
Orlando, United States
2 h-index
6 publications
174 citations

Dankook University
Jukjeon-dong, South Korea
2 h-index
6 publications
112 citations
1–8 of 37
5 publications · 157 citations
5
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Conference · 3 publications · 54 citations
3
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3 publications · 45 citations
3
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2 publications · 30 citations
2
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2 publications · 113 citations
2
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1–5