Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

Abstract

The physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated. We demonstrate that a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and that also the trigger voltage can be easily tuned. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16-20 mA//spl mu/m width have been achieved.