B. Engel

Recent developments in magnetic tunnel junction MRAM

S. Tehrani, B. Engel, J. M. Slaughter et al. · IEEE Transactions on Magnetics · 2000 · 321 citations

Natural Sciences, Electrical Engineering, Materials Science +14

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Engineering, Electrical Engineering, Manufacturing Engineering +11

High performance 14nm SOI FinFET CMOS technology with 0.0174µm ² embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +9

Thermally activated magnetization reversal in submicron magnetic tunnel junctions for magnetoresistive random access memory

N.D. Rizzo, M. DeHerrera, J. Janesky et al. · Applied Physics Letters · 2002 · 101 citations

Natural Sciences, Materials Science, Physics +17

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17