Michael Belyansky

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21

A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

N. Loubet, Subhadeep Kal, Cheryl Alix et al. · 2019 · 81 citations

Engineering, Vlsi Design, Gate-all-around Nanosheet Devices +17

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Timothy A. Brunner, Vinayan C. Menon, Cheuk Wun Wong et al. · Journal of Micro/Nanolithography MEMS and MOEMS · 2013 · 47 citations · Full text

Engineering, Mechanical Engineering, Residual Stress +18