A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

Rakesh Andavarapu, Susmitha Bagati, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Santosh Kumar Padhi, Narendar Vadthiya

IEEE Transactions on Electron Devices · 2023 · 27 citations · 29 references

Abstract

This article for the first time explores the effect of different spacer materials on junctionless (JL) TreeFET for the IRDS sub-5-nm technology node. The study focuses on evaluating the influence of various spacer materials (Air, SiO2, Si3N4, Al2O3, HfO2, and TiO2) on dc and analog/RF performance, considering both single- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> and dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> spacer materials while maintaining a fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {g}}$ </tex-math></inline-formula> = 8 nm and spacer lengths ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula> = 5 and 7 nm). The single- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> spacer analysis demonstrated better dc performances with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> , subthreshold swing (SS), and drain-induced barrier lowering (DIBL) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim &gt; 10^{{8}}$ </tex-math></inline-formula> , ~61 mV/dec, and ~63 mV/V, respectively, at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ext}}=7$ </tex-math></inline-formula> nm, for the TiO2 spacer. The analog parameters <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${A}_{\text {V}}$ </tex-math></inline-formula> , gain frequency product (GFP), and gain transconductance frequency product (GTFP) experienced significant improvements of ~58.7%, ~70.9%, and ~55.95% for the TiO2 spacer at 10-nA normalized drain current. However, the RF parameters, such as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> , tend to be deteriorated by an amount of ~64.5% and ~62.6%, respectively. To further optimize the device performance, four dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> spacer configurations (HfO2 + Air, HfO2 + SiO2, TiO2 + Air, and TiO2 + SiO2) are explored. Specifically, by employing an inner high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> spacer length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {sp},\textit {hk}}{)}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula> /2, notable enhancements are achieved in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${A}_{\text {V}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> , GFP, and GTFP by ~69.5%, ~17.5%, ~27.4%, ~37.7%, and ~36.06%, respectively, making TiO2 + Air dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> spacer suitable for analog/RF applications. The dc performance is also found to be best for this combination too as compared with all other combinations. Particularly, when decreasing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {sp},\textit {hk}}$ </tex-math></inline-formula> from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula> /2 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula> /6, the dc, and analog/RF performances are found to be degraded. Furthermore, the best-optimized device (TiO2+ Air) when implemented to design a CMOS inverter circuit, a voltage gain of ~12 V/V and a delay of 5.32 ps is achieved. Overall, this article pioneers the incorporation of spacer analysis in JL-TreeFET, unveiling its potential for pushing the boundaries of performance and efficiency in modern semiconductor devices.

References

29