Venkata Ramakrishna Kotha

A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

Rakesh Andavarapu, Susmitha Bagati, Sresta Valasa et al. · IEEE Transactions on Electron Devices · 2023 · 27 citations

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Sresta Valasa, Venkata Ramakrishna Kotha, Narendar Vadthiya · ACS Applied Electronic Materials · 2024 · 20 citations

Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications

Sresta Valasa, Venkata Ramakrishna Kotha, Shubham Tayal et al. · IEEE Transactions on Dielectrics and Electrical Insulation · 2024 · 13 citations

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

Chandana Anguru, Vamsi Krishna Aryasomayajula, Venkata Ramakrishna Kotha et al. · ECS Journal of Solid State Science and Technology · 2023 · 11 citations