A Novel SiC Trench MOSFET Embedding Auto-Adjust Source-Potential Region With Switching Oscillation Suppression

Abstract

In this letter, a novel SiC trench MOSFET with integrated auto-adjust source-potential region (AS-TMOS) is proposed and investigated to suppress switching oscillation and reduce turn-off switching loss. The auto-adjust source-potential region, consists of a lightly doped P-base and heavy doped P-shield wrapped around the stepped thick-oxide gate trench, effectively modulates turn-off dV/dt by changing gate-to-drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}{)}$ </tex-math></inline-formula> . Under low applied voltage, a lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}$ </tex-math></inline-formula> is achieved because the deep source-potential region collects the electric field lines that originally contributed to gate-to-drain capacitance. Whereas, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}$ </tex-math></inline-formula> increases more rapidly under high applied voltage due to the source-potential region shrinkage induced by the fully depleted P-base. AS-TMOS under 10 nH stray inductance shows a 28% and 17% reduction of surge voltage and turn-off loss when compared with conventional SiC trench MOSFET (C-TMOS), thus reducing the EMI noise. Furthermore, the short circuit withstanding time of AS-TMOS increases from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu \text{s}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5~\mu \text{s}$ </tex-math></inline-formula> under 800 V DC bus voltage in comparison with C-TMOS owing to the reduction of the peak short circuit current caused by the deep source-potential region.