Dv/dt Reduction

Dv/Dt Reduction is a mitigation technique in power electronics that limits the rate of voltage rise across a switching device to prevent unintended triggering and reduce electromagnetic interference during switching transitions.

159

Publications

6.7K

Citations

493

Authors

162

Institutions

Publications per year

2017–2026

75

Authors

493

  1. PE
    Prasad Enjeti

    Texas A&M University, United States

    7 publications · 720 citations

    7

    h-index

  2. BZ
    Bo Zhang

    University of Electronic Science and Technology of China, China

    4 publications · 73 citations

    4

    h-index

  3. PM
    Pedro Melín

    University of Concepción, Chile

    4 publications · 98 citations

    4

    h-index

  4. JE
    José Espinoza

    University of Concepción, Chile

    4 publications · 98 citations

    4

    h-index

  5. SB
    Subhashish Bhattacharya

    North Carolina State University, United States

    4 publications · 121 citations

    4

    h-index

1–5 of 493

Venues

  1. IEEE Transactions on Power Electronics

    22 publications · 1.8K citations

    18

    h-index

  2. IEEE Transactions on Industrial Electronics

    9 publications · 627 citations

    9

    h-index

  3. IEEE Transactions on Industry Applications

    8 publications · 486 citations

    8

    h-index

  4. IEEE Transactions on Electron Devices

    5 publications · 120 citations

    5

    h-index

  5. IEEE Access

    4 publications · 116 citations

    4

    h-index

1–5