Understanding the Impact of PCB Changes in the Latest Published JEDEC Board Level Drop Test Method

Abstract

Technologies are focusing on empowering consumers with more functionalities into compact assemblies such as ball-grid array (BGA) and Chip Scale Packaging (CSP), offering small form factors to enable high-density semiconductor applications. Reliable performance under drop test conditions is of paramount importance for components targeted for some hand-held applications. Drop testing per JESD22-B111, prescribed by the Joint Electronic Device Engineering Council (JEDEC), is an industrial standard to characterize mechanical reliability of solder joints subject to drop impact under the specified test conditions. This specification was recently revised to JESD22-B111A version, with intent to provide homogenous stress distribution for all components mounted on the newly prescribed PCB layout. The objective of this paper is to assess the impact of these test board changes on drop test performance of solder interconnects and failure modes generated. It is carried out by recording the board dynamic response upon drop impact for test boards with three different form factors. It is complemented well with the Finite Element Modelling (FEM) developed for the studied drop test settings. The investigation is supported by targeted experiments on some prominent package styles. The drop test results show increased characteristic lifetime of solder joints when dropped using the square shaped test board defined by JESD22-B111A as compared to the outstanding studied specifications. This observation is linked to the impact of changing drop impact pulse, PCB form factor and build-up construction on the board dynamics such as resonance frequency modes and PCB deformation.