Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology

Device scaling limits of Si MOSFETs and their application dependencies

D.J. Frank, R.H. Dennard, E. Nowak et al. · Proceedings of the IEEE · 2001 · 1.6K citations

Engineering, Computer Engineering, Electrical Engineering +17

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 758 citations

Engineering, Computer Engineering, Electrical Engineering +16

FinFET scaling to 10 nm gate length

Bin Yu, Leland Chang, Safayet Ahmed et al. · 2003 · 595 citations

Engineering, Electrical Engineering, Microelectronics +15

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain et al. · 2012 · 305 citations

Engineering, Computer Engineering, Electrical Engineering +16

Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design

Brad D. Gaynor, Soha Hassoun · IEEE Transactions on Electron Devices · 2014 · 90 citations

Engineering, Computer Engineering, Electrical Engineering +17