Device scaling limits of Si MOSFETs and their application dependencies

TLDR

The physical origins of these limits are primarily in the tunneling currents that leak through the barriers in a MOSFET when it becomes very small, and in the thermally generated sub‑threshold currents. This paper presents the current state of understanding of the factors that limit the continued scaling of Si CMOS technology and analyzes how application‑related considerations influence these limits. The authors discuss how leakage currents depend on MOSFET geometry and structure, the design criteria for minimizing short‑channel effects, and the application‑related constraints on power consumption and circuit functionality, with examples for DRAM, SRAM, low‑power portable devices, and high‑performance CMOS logic. They estimate scaling limits for various applications and device types, concluding that there is no single endpoint for scaling but rather multiple application‑specific endpoints.

Abstract

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.