FOWLP electrical performances

Abstract

Fan Out-Wafer Level Packaging (FO-WLP) has been recognized as the main electronic packaging and integration technology. It is cost effective and has good electrical performance as compared to the Silicon Interposer. Currently, there are many different versions of this FO-WLP technology being developed with the objective to increase the routing density. In order to design integrated circuit or package the electrical chip using the FO-WLP, it is essential to characterize electrical parameters. In this paper, the Redistribution Layers (RDL) first version of the FO-WLP electrical parameters and their test structures are provided.