Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

TLDR

Fan‑out Wafer Level Packaging (FOWLP) is emerging for consumer electronics but conventional designs are limited to small, single‑chip packages with low‑to‑mid I/O counts due to die shift, warpage, and RDL scaling issues. This work introduces an RDL‑First FOWLP approach that scales RDL, mitigates die shift, protrusion, and warpage, enabling multi‑chip, high‑I/O packages. The authors fabricated a 20 × 20 mm multi‑chip test vehicle with a 3‑layer fine‑pitch RDL (~2400 I/Os), evaluated tall‑Cu pillar and vertical‑Cu wire through‑mold interconnections, implemented backside RDL on over‑molded C2W, and established laser debonding, sacrificial release, and optimized assembly to demonstrate PoP integration. The resulting packages passed JEDEC Moisture Sensitivity Test Levels 1 and 3 and survived 30 board‑level drop tests, confirming the viability of the RDL‑First FOWLP process.

Abstract

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.