Scan-Chain Intra-Cell Aware Testing

Abstract

This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46 percent on average) and a shorter test time (i.e., 42.20 percent on average) than by straightforwardly using an ATPG which directly targets these defects.