A buried-trench DRAM cell using a self-aligned epitaxy over trench technology

Abstract

A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of the cell horizontal access transistor in bulk material epitaxially grown over the trench capacitor. The via connection between the access transistor and the buried trench is a vertical sublithographic contact self-aligned to the trench. This BT cell, with a minimum of 10.8 lithographic squares, was fabricated in a submicron n-well epitaxial CMOS process incorporating the SEOT technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>