Highly Scalable Raised Source/Drain InAs Quantum Well MOSFETs Exhibiting <inline-formula> <tex-math notation="TeX">$I_{{\scriptstyle {\rm ON}}}=482~\mu{\rm A}/\mu{\rm m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="TeX">$I_{{\scriptstyle {\rm OFF}}}=100~{\rm nA}/\mu{\rm m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="TeX">$V_{\rm DD}=0.5~{\rm V}$ </tex-math></inline-formula>

Abstract

We report raised source/drain (S/D) InAs quantum well MOSFETs incorporating a vertical spacer formed by metal-organic chemical vapor deposition epitaxial regrowth. By adopting a 12-nm-thick vertical spacer between the channel and the N+ S/D, OFF-state characteristics are significantly improved. A device with a 40-nm-Lg and 12-nm-thick spacer shows 2.5-mS/μm peak transconductance (gm), 86-mV/decade subthreshold swing at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V, 83-mV/V drain-induced barrier lowering, and 482-μA/μm ON-current at 100-nA/μm OFF-current and VDD = 0.5 V. In addition, a 3.0-mS/μm peak gm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V is achieved in an 18-nm-Lg device with a 2-nm-thick spacer, the highest reported peak gm of any field-effect transistor.