IEEE Journal of Solid-State Circuits · 2003 · 21 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCachingCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyLeakage Power ReductionLow-power Cache DesignMemory Subsystem DesignArea Overhead AnalysisCache DesignCache Leakage ReductionCache Memory DesignHigh PerformanceHigh-frequency PerformanceLeakage-aware Cache DesignLeakage-aware Memory Design
This work describes an aggressive SRAM cell configuration using dual-V/sub T/ and minimum channel length to achieve high performance. A bitline leakage reduction technique is incorporated into an L1 cache design using the new cell in a 100-nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6-GHz operation at with 15% higher energy.
6