Hiroyuki Hara

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

M. Matsui, Hiroyuki Hara, Yoshiharu Uetani et al. · IEEE Journal of Solid-State Circuits · 1994 · 146 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara et al. · 2011 · 114 citations

Engineering, Computer Engineering, Electrical Engineering +17

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Hiroki Noguchi, Kazutaka Ikegami, K. Kushida et al. · 2015 · 97 citations

Engineering, Computer Engineering, Electrical Engineering +17

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory

Tomoharu Tanaka, Yasunori Tanaka, Hiroki Nakamura et al. · IEEE Journal of Solid-State Circuits · 1994 · 86 citations

Engineering, Computer Engineering, Computer Science +14

50% active-power saving without speed degradation using standby power reduction (SPR) circuit

K. Seta, Hiroyuki Hara, Tadahiro Kuroda et al. · 2002 · 77 citations

Engineering, Computer Engineering, Electrical Engineering +17