7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

TLDR

Spin‑transfer torque magnetoresistive RAM (STT‑MRAM) is pursued as a nonvolatile, high‑speed, CMOS‑compatible memory, but its high‑speed operation raises read‑disturb risk and demands lower programming, active, and peripheral leakage currents. This work aims to mitigate read‑disturb, reduce active charging power, and lower peripheral leakage in high‑speed STT‑MRAM through novel circuit designs. The authors implement a short read‑pulse generator using a hierarchical bitline to eliminate read disturbance, a charge‑optimization scheme to limit active power, and ultra‑fast power‑gating with adaptive power‑on to suppress leakage. The resulting 1 Mb STT‑MRAM achieves sub‑5 ns access times and roughly three‑fold power savings compared to SRAM for last‑level cache.

Abstract

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ∼3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.