Atsushi Kawasumi

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Hiroki Noguchi, Kazutaka Ikegami, K. Kushida et al. · 2015 · 97 citations

Engineering, Computer Engineering, Electrical Engineering +17

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki et al. · 2009 · 92 citations

Engineering, Computer Engineering, Electrical Engineering +14

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya et al. · 2016 · 69 citations

Engineering, Computer Engineering, Computer Science +17

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Hiroki Noguchi, K. Kushida, Kazutaka Ikegami et al. · 2013 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano et al. · IEEE Journal of Solid-State Circuits · 2009 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17