7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Hiroki Noguchi, Kazutaka Ikegami, K. Kushida, +8

Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture +18

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki, +10

Low-power ElectronicsLevel-programmable Wordline DriverElectrical EngineeringProcess-variation-tolerant Dual-power-supply SramKb Dual-power-supply Sram +8

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, +10

Non-volatile MemoryElectrical EngineeringEngineeringPerformance GapsStt-mram-based Cache +10

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Hiroki Noguchi, K. Kushida, Kazutaka Ikegami, +7

MagnetismElectrical EngineeringNon-volatile MemoryNovel 1MbEngineering +11

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano, +7

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringNovel Sram ArchitectureEngineeringVlsi Design +8

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, +8

Non-volatile MemoryElectrical EngineeringMetal-gate CmosEngineeringVlsi Design +11

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, +6

IEEE Journal of Solid-State Circuits

Low-power ElectronicsRandom-variation-tolerant Timing GenerationElectrical EngineeringEngineeringVlsi Design +13

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Atsushi Kawasumi, Tomoaki Yabe, Y. Takeyama, +8

Low-power ElectronicsElectrical EngineeringBulk SramVlsi DesignEngineering +10

A Low Leakage SRAM Macro With Replica Cell Biasing Scheme

Y. Takeyama, Hiroyuki Otake, Osamu Hirabayashi, +2

IEEE Journal of Solid-State Circuits

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringReplica Cell +8

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Kazutaka Ikegami, Hiroshi Noguchi, C. Kamata, +13

Low PowerNon-volatile MemoryElectrical EngineeringEngineeringCircuit Design +11