Osamu Hirabayashi

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki et al. · 2009 · 92 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano et al. · IEEE Journal of Solid-State Circuits · 2009 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki et al. · 2010 · 46 citations

Engineering, Computer Engineering, Electrical Engineering +15

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki et al. · IEEE Journal of Solid-State Circuits · 2011 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +15

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Atsushi Kawasumi, Tomoaki Yabe, Y. Takeyama et al. · 2008 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +14